1. Field of the Invention
The present invention is directed in general to the field of semiconductor devices. In one aspect, the present invention relates to field effect transistors (FETs) fabricated on hybrid or dual substrates.
2. Description of the Related Art
To address the difference in electron and hole mobility values for NMOS and PMOS transistor devices formed on semiconductor wafers having a single crystal orientation, CMOS devices are increasingly fabricated with hybrid substrates with different or dual surface orientations (DSO) using semiconductor-on-insulator (SOI) or bulk silicon wafer bonding to provide PMOS and NMOS devices with their own optimized crystal orientation. Prior attempts to integrate dual or hybrid substrates from a bonded SOI wafer have etched through the buried oxide layer to expose an underlying silicon layer which is used to epitaxially grow one of the crystal surface orientations, but have resulted in non-uniform silicon step/recess heights between the different crystal surfaces which require an additional chemical mechanical polish (CMP) step. An example is depicted in FIGS. 1-3 which show a device 10 having two crystal surface orientations—surface 7 having a first orientation and a semiconductor-on-insulator (SOI) layer 3 having a second orientation—separated by buried oxide layers 2 and isolation regions 4 and covered by nitride layers 6. As shown in FIG. 1, an epi silicon layer 7 (having the first orientation) is formed in an opening in the device 10, which itself was formed by etching through the SOI layer 3 and buried oxide layer 2 to expose a portion of the substrate 1. After the epi silicon 8 is polished (as depicted in FIG. 2), the surface of the epi silicon 8 is recessed below the nitride layer 6. However, when the nitride layer 6 is stripped (as depicted in FIG. 3), the epi silicon 8 is higher than the underlying SOI layer 3. To planarize the SOI layer 3 and epi silicon 8 layer, an additional CMP step is required. The collection of etch, epitaxial growth and CMP steps required to obtain uniform surface heights adds significant cost and complexity to the device fabrication. One approach to reduce the different DSO surface heights is to form a bulk wafer by bonding two bulk wafers with no interfacial oxide. However, the silicon-to-silicon bond is a challenging semiconductor process which creates dislocations at the interface which can affect device performance if too close to the active channel regions. These dislocations can be reduced by using high energy implants to amorphize the silicon and then re-crystallizing the silicon with an anneal process, though these additional processing steps also add the cost and complexity of the device fabrication.
Accordingly, a need exists for a cost effective semiconductor manufacturing process which provides the process and performance advantages of forming a bulk hybrid orientation substrate. There is also a need for a fabrication process which avoids the process and performance limitations associated with non-uniform surface heights and minimizes surface step heights in a Dual-Surface Orientation (DSO) integration. In addition, there is a need for improved semiconductor processes and devices to overcome the problems in the art, such as outlined above. Further limitations and disadvantages of conventional processes and technologies will become apparent to one of skill in the art after reviewing the remainder of the present application with reference to the drawings and detailed description which follow.
It will be appreciated that for simplicity and clarity of illustration, elements illustrated in the drawings have not necessarily been drawn to scale. For example, the dimensions of some of the elements are exaggerated relative to other elements for purposes of promoting and improving clarity and understanding. Further, where considered appropriate, reference numerals have been repeated among the drawings to represent corresponding or analogous elements.